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Genesys Logic, Inc. Today announced its high-performance USB 3.0 hub controller, GL3520, was certified by the USB Implementers Forum (USB-IF). When I plug in a usb 3 hub, external harddrives get splicing input. Bus 001 Device 002: ID 05e3:0606 Genesys Logic, Inc.

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1 Genesys Logic, Inc. GL3520 USB 3.0 Hub Controller Datasheet Revision 1.32 Jul. 15, 2011

2 Copyright Copyright 2011 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Ownership and Title Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder. Disclaimer All Materials are provided as is. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice. Genesys Logic, Inc. 12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231, New Taipei City, Taiwan Tel : (886-2) Fax : (886-2) Genesys Logic, Inc. - All rights reserved. Page 2

3 Revision History Revision Date Description /24/2011 First formal release /20/2011 Update QFN64 pin assignment /17/2011 Modify QFN88 package dimension, p.31 Modify Table 7.2-Operating Ranges, p /23/2011 Modify QFN64 package dimension, p /10/2011 Revise typo, p /17/2011 Update CH7.4 Power Consumption, p.26, /24/2011 Update crystal tolerance range, p /15/2011 Update CH3.2 Pin Descriptions, RTERM I/O type, p Genesys Logic, Inc. - All rights reserved. Page 3

4 Table of Contents CHAPTER 1 GENERAL DESCRIPTION.. 7 CHAPTER 2 FEATURES.. 8 CHAPTER 3 PIN ASSIGNMENT Pinout Pin Descriptions CHAPTER 4 BLOCK DIAGRAM CHAPTER 5 FUNCTION DESCRIPTION General Description USB 2.0 USPORT Transceiver USB 3.0 USPORT Transceiver PLL (Phase Lock Loop) Regulator SPI Engine RAM/ROM/CPU UTMI (USB 2.0 Transceiver Microcell Interface) SIE (Serial Interface Engine) Control/Status Register Power Management Engine Router/Aggregator Engine REPEATER TT CDP Control Logic USB 3.0/USB 2.0 DSPORT Transceiver Configuration and I/O Settings RESET Setting PGANG Setting SELF/BUS Power Setting LED Connections Power Switch Enable Polarity Port Number Configuration Non-removable Port Configuration Genesys Logic, Inc. - All rights reserved. Page 4

5 CHAPTER 6 USB-IF BATTERY CHARGING SPECIFICATION REV.1.1 SUPPORT Background Charging Downstream Port (CDP) Charging Detection Hardware Handshaking Dedicated Charging Port (DCP) Port Numbers of Charging Downstream Port Configuration CHAPTER 7 ELECTRICAL CHARACTERISTICS Maximum Ratings Operating Ranges DC Characteristics DC Characteristics except USB Signals USB 2.0 Interface DC Characteristics USB 3.0 Interface DC Characteristics Power Consumption AC Characteristics On-Chip Power Regulator CHAPTER 8 PACKAGE DIMENSION CHAPTER 9 ORDERING INFORMATION Genesys Logic, Inc. - All rights reserved. Page 5

6 List of Figures Figure GL3520 QFN 88 Pin Pinout Diagram.. 9 Figure GL3520 QFN 64 Pin Pinout Diagram Figure Block Diagram Figure Operating in USB 1.1 Schemes Figure Operating in USB 2.0 Schemes Figure Power on Reset Diagram Figure Power on Sequence of GL Figure Timing of PGANG Strapping Figure GANG Mode Setting Figure SELF/BUS Power Setting Figure LED Connection Figure Vin(V5) vs Vout(V33)* Figure GL Pin QFN Package Figure GL Pin QFN Package List of Tables Table Configuration by Power Switch Type Table Maximum Ratings Table Operating Ranges Table DC Characteristics except USB Signals Table Ordering Information Genesys Logic, Inc. - All rights reserved. Page 6

7 CHAPTER 1 GENERAL DESCRIPTION GL3520 is a highly-compatible, high performance USB 3.0 hub controller, which integrates Genesys Logic own self-developed USB 3.0 Super Speed transmitter/receiver physical layer (PHY) and USB 2.0 High-Speed PHY. It supports Super Speed, Hi-Speed, and Full-Speed USB connections and is fully backward compatible to all USB 2.0 and USB 1.1 hosts. GL3520 is a premium 4 port MTT Hub solution, implementing multiple TT* (Note1) architecture that provide dedicated TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple FS device perform heavy loading operations. GL3520 also complies with USB-IF battery charging specification rev1.1, which can support fast charging function, allowing portable device can draw up to 1.5A from GL3520 charging downstream ports (CDP 1 ) or dedicated charging port (DCP 2 ). So it can enable systems to fast charge handheld devices even during Sleep and Power-off modes. There are two available packages: QFN88(10x10mm) and QFN64(8x8mm). Summarize as below table. Package Type # of DS Ports Power Mgmt. LED Support FW Upgrade QFN 88 4 Individual/Gang Green/Amber SPI Flash QFN 64 4 Gang Green SPI Flash GL3520 Package Feature Summary *Note: TT (transaction translator) implements the control logic defined in section ~ of USB specification revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. 1 CDP, charging downstream port, the Battery Charging Rev.1.1-compliant USB port that does data communication and charges device up to 1.5A. 2 DCP, dedicated charging port, the Battery Charging Rev.1.1-compliant USB port that only charges devices up to 1.5A, similar to wall chargers Genesys Logic, Inc. - All rights reserved. Page 7

8 CHAPTER 2 FEATURES Compliant with USB Specification Revision Upstream port supports super speed(ss) high speed(hs) and full speed(fs) traffic - Downstream ports support SS, HS, FS, and low speed(ls) traffic - 1 control pipe(endpoint 0, 64-byte data payload) and 1 interrupt pipe(endpoint 1, 1-byte data payload) - Backward compatible to USB specification Revision 2.0/1.1 Compliant with USB Battery Charging Revision v1.1 - Turning its downstream port from a standard downstream port (SDP) into charging downstream port (CDP) or Dedicated Charging Ports (DCP). - Enables portable device to charge from VBUS even when the USB bus is in suspend. On-chip 8-bit micro-processor - RISC-like architecture - USB optimized instruction set - 1 cycle instruction execution( maximum) - Performance: 12 12MHz( maximum) - With 256-byte RAM, 16K-byte internal ROM & 16K-byte SRAM Multi Transaction Translator(TT) architecture - Provides dedicated TT control logics for each downstream port - Superior performance when multiple FS devices operate concurrently Integrated USB transceiver - Improve output drivers with slew-rate control for EMI reduction - Internal power-fail detection for ESD recovery Smart power management - Support USB3.0 U0/U1/U2/U3 power management states - Support individual / gang mode over-current detection for all downstream ports. - Support both low/high-enabled power switches. - Automatic switching between self-powered and bus-powered modes. Low BOM cost - Single external 25 MHz crystal / Oscillator clock input - Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors Flexible design - Configurable 4/3/2 downstream ports - Support partial/full in-system programming firmware upgrade by SPI-flash - Support compound-device (non-removable in downstream ports) by I/O pin configuration Available package type - QFN 88 (10x10mm) - QFN 64 (8x8mm) Applications: - Stand-alone USB hub / USB docking - Netbook/Smartbook/MID/Motherboard on-board applications - Monitor built-in hub - TV built-in hub - Other Consumer electronics built-in hub application - Compound device to support USB hub function such as hub reader applications 2011 Genesys Logic, Inc. - All rights reserved. Page 8

9 CHAPTER 3 PIN ASSIGNMENT 3.1 Pinout QFN DVDD12 VP12 RXP_DS4 RXN_DS4 GND TXP_DS4 TXN_DS4 VP12 VP12 RXP_DS3 RXN_DS3 GND TXP_DS3 TXN_DS3 VP12 VP12 RXP_DS2 RXN_DS2 GND TXP_DS2 TXN_DS2 VP12 PAMBER4 PWREN4J RTERM GND VP33CR X1 X2 VP12 TXN_UP TXP_UP GND RXN_UP RXP_UP VP12 VP12 TXN_DS1 TXP_DS1 GND RXN_DS1 RXP_DS1 VP12 GND AVDD DP2 DM2 AVDD DP1 DM1 DP0 DM0 DVDD DVDD12 PAMBER3 VBUS OVCUR4J PWREN1J PAMBER1 P_SPI_CZ P_SPI_CK DVDD12 PGREEN3 PWREN3J PWREN2J OVCUR2J GND DM3 DP3 AVDD DM4 DP4 DVDD PGANG DVDD12 TEST OVCUR3J OVCUR1J PGREEN1 P_SPI_DO P_SPI_DI PSELF RESETJ PGREEN2 V33 V5 PAMBER2 PGREEN Figure GL3520 QFN 88 Pin Pinout Diagram 2011 Genesys Logic, Inc. - All rights reserved. Page 9

10 DM3 DP3 AVDD DM4 DP4 DVDD PGANG DVDD12 OVCUR1J P_SPI_DO P_SPI_DI PSELF RESETJ DVDD12 V33 V QFN RXN_DS4 TXP_DS4 TXN_DS4 VP12 VP12 RXP_DS3 RXN_DS3 TXP_DS3 TXN_DS3 VP12 VP12 RXP_DS2 RXN_DS2 TXP_DS2 TXN_DS2 VP12 Figure GL3520 QFN 64 Pin Pinout Diagram 2011 Genesys Logic, Inc. - All rights reserved. Page 10

11 3.2 Pin Descriptions USB Interface Pin Name QFN 88 QFN 64 Type Description TXN_UP 9 6 TXP_UP 10 7 O USB 3.0 Differential Data Transmitter TX-/TX+ of USPORT RXN_UP 12 8 RXP_UP 13 9 I USB 3.0 Differential Data Receiver RX-/RX+ of USPORT TXN_DS TXP_DS O USB 3.0 Differential Data Transmitter TX-/TX+ of DSPORT1 RXN_DS RXP_DS I USB 3.0 Differential Data Receiver RX-/RX+ of DSPORT1 TXN_DS TXP_DS O USB 3.0 Differential Data Transmitter TX-/TX+ of DSPORT2 RXN_DS RXP_DS I USB 3.0 Differential Data Receiver RX-/RX+ of DSPORT2 TXN_DS TXP_DS O USB 3.0 Differential Data Transmitter TX-/TX+ of DSPORT3 RXN_DS RXP_DS I USB 3.0 Differential Data Receiver RX-/RX+ of DSPORT3 TXN_DS TXP_DS O USB 3.0 Differential Data Transmitter TX-/TX+ of DSPORT4 RXN_DS RXP_DS I USB 3.0 Differential Data Receiver RX-/RX+ of DSPORT4 DM0,DP0 59, B USB 2.0 DM/DP for USPORT DM1, DP1 61, B USB 2.0 DM/DP for DSPORT1 DM2, DP2 64, B USB 2.0 DM/DP for DSPORT2 DM3, DP3 68, B USB 2.0 DM/DP for DSPORT3 DM4, DP4 71, B USB 2.0 DM/DP for DSPORT4 Hub Interface Pin Name QFN 88 QFN 64 Type Description PGREEN1~4 79,84, 48,88 - B (pd) Green LED indicator for DSPORT1~4 PAMBER1~4 52,87,56,1 - B (pd) Amber LED indicator for DSPORT1~4 PWREN1~4J 53,46,47,2 37, B Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for GANG mode. OVCUR1~4J 78,45,77,5 Active low. Over current indicator for DSPORT1~4 57 I (pu) 4 OVCUR1# is the only over current flag for GANG mode. PGANG I Default put in input mode after power-on reset. Individual/gang mode is strapped during this period. PSELF I 0: GL3520 is bus-powered. 1: GL3520 is self-powered Genesys Logic, Inc. - All rights reserved. Page 11

12 Clock and Reset Interface Pin Name QFN 88 QFN 64 Type Description X1 6 3 I Crystal / OSC clock input X2 7 4 O Crystal clock output. RESETJ I (pd) Active low. External reset input, default pull high 10KΩ. When RESET# = low, whole chip is reset to the initial state. SPI Interface Pin Name QFN 88 QFN 64 Type Description P_SPI_CK B For SPI data clock P_SPI_CZ B For SPI data chip enable P_SPI_DO B For SPI data Input P_SPI_DI B For SPI data Output Power/Ground Interface Pin Name QFN 88 QFN 64 Type Description VP33CR 5 2 P Analog 3.3V power input 8,14,15,21,23 5,10.11,1617,2 VP12 P Analog 1.2V power input for Analog circuit 29,30,36,37,43 2,23,28,29,34 DVDD12 44,49,57,75 39,56,62 P 1.2V digital power input for digital circuits DVDD 58,73 40,54 P 3.3V digital power input for digital circuits AVDD 63,66,70 45,48,51 P Analog 3.3V power input GND 4,11,18,22 26,33,40,67 - P Digital/Analog ground VBUS I VBUS valid input V P 5V-to-3.3V regulator Vout & 3.3 input V P 5V Power input. It need be NC if using external regulator Miscellaneous Interface Pin Name QFN 88 QFN 64 Type Description RTERM 3 1 A A 680ohm resister must be connected between RTERM and Ground TEST: 0: Normal operation. TEST 76 - B (pd) 1: Chip will be put in test mode. Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL3520 Design Guideline. Notation: Type O Output I Input B Bi-directional P Power / Ground A Analog 2011 Genesys Logic, Inc. - All rights reserved. Page 12

13 pu pd Internal pull up Internal pull down 2011 Genesys Logic, Inc. - All rights reserved. Page 13

14 CHAPTER 4 BLOCK DIAGRAM Figure Block Diagram 2011 Genesys Logic, Inc. - All rights reserved. Page 14

15 CHAPTER 5 FUNCTION DESCRIPTION 5.1 General Description USB 2.0 USPORT Transceiver USB 2.0 USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL3520 is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL3520 is plugged into a 2.0 host/hub USB 3.0 USPORT Transceiver USB 3.0 USPORT (upstream port) transceiver is the analog circuit that has elastic buffer and supports receiver detection, data serialization and de-serialization. Besides, it has PIPE interface with SuperSpeed Link Layer PLL (Phase Lock Loop) PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter Regulator GL3520 build in internal regulator converts 5V input to 3.3V output SPI Engine SPI engine is to move code from external flash to the internal RAM RAM/ROM/CPU The micro-processor unit of GL3520 is an 8-bit RISC processor with 16K-byte ROM and 256-bytes RAM. It operates at 12MIPS of 12 MHz clock( maximum) to decode the USB command issued from host and then prepares the data to respond to the host UTMI (USB 2.0 Transceiver Microcell Interface) UTMI handles the low level USB protocol and signaling. It s designed based on the Intel s UTMI specification The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion SIE (Serial Interface Engine) SIE handles the USB protocol defined in chapter 8 of USB specification revision 2.0. It co-works with μc to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE Control/Status Register Control/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL3520 possesses higher flexibility to control the USB protocol easily and correctly Genesys Logic, Inc. - All rights reserved. Page 15

16 Power Management Engine The power management of GL3520 is compliant with USB 3.0 specification. When operates in SuperSpeed mode, GL3520 supports U0, U1, U2 and U3 power states. U0 is the functional state. U1 and U2 are lower power states compared to U0. U1 is a low power state with fast exit to U0; U2 is a low power state which saves more power than U1, with slower exit to U0. U3 is suspend state, which is the most power-saving state, with tens of milliseconds exit to U0. Unlike USB 2.0, SuperSpeed packet traffic is unicast rather than broadcast. Packet only travels the direct path in-between host and the target device. SuperSpeed traffic will not reach an unrelated device. When enabled for U1/U2 entry, and there is no pending traffic within comparable exit latency, GL3520 will initiate U1/U2 entry to save the power. On the other hand, the link partner of GL3520 may also initiate U1/U2 entry. In this case, GL3520 will accept or reject low power state entry according to its internal condition Router/Aggregator Engine Router/Aggregator Engine implement the control logic defined in Ch10 of USB3.0 specification. Router/Aggregator Engine use smart method for route packet to device or aggregate packet to host REPEATER Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended TT TT(Transaction Translator) implements the control logic defined in section ~ of USB specification revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL3520 adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively Connected to 1.1 Host/Hub If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER Genesys Logic, Inc. - All rights reserved. Page 16

17 USB 1.1 Host/Hub USPORToperating in FS signaling Traffic channel is routed to REPEATER REPEATER TT TT DSPORT operating in FS/LS signaling Figure Operating in USB 1.1 Schemes Connected to USB 2.0 Host/Hub If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed Genesys Logic, Inc. - All rights reserved. Page 17

18 USB 2.0 Host/Hub USPORToperating in HS signaling HS vs. HS: Traffic channel is routed to REPEATER REPEATER TT TT HS vs. FS/LS: Traffic channel is routed to TT DSPORT operating in HS signaling DSPORT operating in FS/LS signaling Figure Operating in USB 2.0 Schemes CDP Control Logic CDP (charging downstream port) control logic implements the logic defined in USB Battery charging specification revision 1.1. The major function of it is to control DSPORT Transceiver to make handshake with a portable device which is compliant with USB Battery charging spec rev1.1 as well. After recognizing charging detection each other, portable device will draw up to 1.5A from VBUS to fast charge its battery USB 3.0/USB 2.0 DSPORT Transceiver DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices Genesys Logic, Inc. - All rights reserved. Page 18

19 5.2 Configuration and I/O Settings RESET Setting GL3520 s power on reset can either be triggered by external reset or internal power good reset circuit. The external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested value refers to schematics) GL3520 s internal reset is designed to monitor silicon s internal core power (1.2V) and initiate reset when unstable power event occurs. The power on sequence will start after the power good voltage has been met, and the reset will be released after approximately 40 μs after power good. GL3520 s reset circuit as depicted in the picture. VBUS (External 5V) PCB R1 Silicon Ext. VBUS power-good detection circuit input (Pin'RESET#') R2 EXT INT Global Reset# Pin VBUS Int. 3.3V power-good detection circuit input (USB PHY reset) Figure Power on Reset Diagram To fully control the reset process of GL3520, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure. Figure Power on Sequence of GL Genesys Logic, Inc. - All rights reserved. Page 19

20 5.2.2 PGANG Setting To save pin count, GL3520 uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 21us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL3520 outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100KΩ should be placed. For gang mode, a pull high resister which greater than 100KΩ should be placed. In figure 5.6, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA). Figure Timing of PGANG Strapping Figure GANG Mode Setting 2011 Genesys Logic, Inc. - All rights reserved. Page 20

21 5.2.3 SELF/BUS Power Setting By setting PSELF, GL3520 can be configured as a bus-power or a self-power hub. Figure SELF/BUS Power Setting LED Connections GL3520 controls the LED lighting according to the flow defined in section of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL3520. When GL3520 is globally suspended, GL3520 will turn off the LED to save power. AMBER/GREEN LED DGND Inside GL3520 On PCB Figure LED Connection Power Switch Enable Polarity Both low/high-enabled power switches are supported. It is determined by jumper setting. The power switch polarity will be configured by the state of pin AMBER2, as the following table: Table Configuration by Power Switch Type AMBER2 0 Low-active 1 High-active Power Switch Enable Polarity Note: When AMBER2=1, the external resistor of PWREN1~4 need pull down 2011 Genesys Logic, Inc. - All rights reserved. Page 21

22 5.2.6 Port Number Configuration Number of downstream port can be configured as 1/2/3/4 ports by firmware configuration. The detail setting information please refers to the GL3520 Firmware ISP Tool User Guide document Non-removable Port Configuration For compound application or embedded system, downstream ports that always connected inside the system can be set as non-removable by firmware configuration. The detail setting information please refers to the GL3520 Firmware ISP Tool User Guide document Genesys Logic, Inc. - All rights reserved. Page 22

23 CHAPTER 6 USB-IF BATTERY CHARGING SPECIFICATION REV.1.1 SUPPORT 6.1 Background The USB ports on personal computers are convenient places for portable devices to draw current for charging their batteries. This convenience has led to the creation of dedicated chargers that simply expose a USB standard-a receptacle. This allows portable devices to use the same USB cable to charge from either a PC or from a dedicated charger. If a portable device is attached to a USB host or hub, then the USB 2.0 specification requires that after connecting, a portable device must draw less than: 2.5 ma average if the bus is suspended 100 ma maximum if bus is not suspended and not configured 500 ma maximum if bus is not suspended and configured for 500 ma If a portable device is attached to a charging host or hub, it is allowed to draw a current up to 1.5A or 900mA, regardless of suspend. In order for a portable device determine how much current it is allowed to draw from an upstream USB port, the USB-IF Battery Charging specification defines the mechanisms that allow the portable device to distinguish between either a USB standard host, hub or a USB charging host. Since portable device can be attached to USB charging ports from various manufactures, it is important that all USB charging ports behave the same way. This specification also defines the requirements for a USB chargers and charging downstream ports. 6.2 Charging Downstream Port (CDP) GL3520 supports battery charging detection, turning its downstream port from a standard downstream port (SDP) into charging downstream port (CDP). GL3520 will make physical layer handshaking when a portable device (PD) compliant with BC rev1.1 attaches to its downstream port. After physical layer handshaking, PD is allowed to draw more current up to 900mA or 1.5A, depending on PD is configured as High-Speed (900mA) or Full-Speed/Low-Speed (1.5A) device. 6.3 Charging Detection Hardware Handshaking Once the charging downstream port of GL3520 enabled, it will monitor the V DP_SRC on D+ line anytime. When BCv1.1 compliant PD attached to the downstream port, it will drive V DP_SRC on D+ line to initiate handshaking with charging downstream port. GL3520 will response on its D- line by V DM_SRC and keep in a certain period of time and voltage level. The portable device will accept this handshake on its D- line in correct timing period and voltage level and then turns off its V DP_SRC on D+ line. GL3520 will recognize that charging negotiation is finished by counting time between PD turning on and off its V DP_SRC. After that, the portable device can start to draw more current at VBUS to charge its battery more rapidly. It can draw current up to 1.5A or 900mA, depending on PD is configured as HS, FS or LS device. If no response on D- line returns, the portable device will recognize that it is attached to a standard downstream port, not a charging port Genesys Logic, Inc. - All rights reserved. Page 23

24 6.4 Dedicated Charging Port (DCP) GL3520 also support dedicated charging port, which is a downstream port on a device that outputs power through a USB connector, but is not capable of enumerating a downstream device. With the adequate system circuit design, GL3520 will turn its downstream port from a standard downstream port (SDP) into dedicated charging port (DCP), i.e short the D+ line to the D- line, to let PD draw current up to 1.5A. The detail system design information please refers to the GL3520 Design Guide document. 6.5 Port Numbers of Charging Downstream Port Configuration Numbers of charging downstream port can be configured as 1/2/3/4 ports by firmware configuration. The detail setting information please refers to the GL3520 Firmware ISP Tool User Guide document Genesys Logic, Inc. - All rights reserved. Page 24

25 CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 Maximum Ratings Table Maximum Ratings Symbol Parameter Min. Max. Unit V 5 5V Power Supply V V DD 3.3V Power Supply V VDDcore 1.2VPower Supply V V IN 3.3V Input Voltage for digital I/O(EE_DO) pins V Vincore 1.2V V V INOD Open-Drain Input (Ovcur1-4,Pself,Reset) V V INUSB Input Voltage for USB signal (DP, DM) pins V T S Storage Temperature under bias F OSC Frequency 25 MHz 0.03% o C 7.2 Operating Ranges Table Operating Ranges Symbol Parameter Min. Typ. Max. Unit V 5 5V Power Supply V V DD 3.3V Power Supply V VDDcore 1.2V Power Supply V V IND Input Voltage for digital I/O pins V V INUSB Input Voltage for USB signal (DP, DM) pins V T A Ambient Temperature 0-70 T J Absolute maximum junction temperature o C o C 2011 Genesys Logic, Inc. - All rights reserved. Page 25

26 7.3 DC Characteristics DC Characteristics except USB Signals Table DC Characteristics except USB Signals Symbol Parameter Min. Typ. Max. Unit V DD Power Supply Voltage V V IL LOW level input voltage V V IH HIGH level input voltage V V TLH LOW to HIGH threshold voltage V V THL HIGH to LOW threshold voltage V V OL LOW level output voltage when I OL =8mA V V OH HIGH level output voltage when I OH =8mA V I OLK Leakage current for pads with internal pull up or pull down resistor A R DN Pad internal pull down resister 81K 103K 181K Ω R UP Pad internal pull up resister 81K 103K 181K Ω USB 2.0 Interface DC Characteristics The GL3520 conforms to DC characteristics for Universal Serial Bus specification rev Please refer to this specification for more information USB 3.0 Interface DC Characteristics The GL3520 conforms to DC characteristics for Universal Serial Bus specification rev.3.0. Please refer to this specification for more information. 7.4 Power Consumption Symbol USB 3.0 Host Number of USB 3.0 Active Ports Config. Read Write Unit W W I CC W W USPORT Config 0.01 W 2011 Genesys Logic, Inc. - All rights reserved. Page 26

27 Symbol I CC USB 3.0 Host Number of USB 2.0 Active Ports Config. Read Write Unit W W W W USPORT Config 0.01 W Note: Test result represents silicon level operating current, without considering additional power consumption contributed by external over-current protection circuit such as power switch or polyfuse Genesys Logic, Inc. - All rights reserved. Page 27

28 7.5 AC Characteristics GL3520 can support SPI( mode0) for on-line firmware upgrade Genesys Logic, Inc. - All rights reserved. Page 28

29 Symbol Parameter Min. Typ. Max. Unit f CT Clock Frequency for fast read mode MHz f C Clock Frequency for read mode 0-33 MHz t RI Input Rise Time ns t FI Input Fall Time ns t CXH SCK High Time ns t CXL SCK Low Time ns t CEH CE# High Time ns t CS CE# Setup Time ns t CH CE# Hold Time ns t DS Data in Setup Time ns t DH Data in Hold Time ns t HS Hold Setup Time ns t HD Hold Time ns t V Output Valid ns t OH Output Hold Time Normal Mode ns t LZ Hold to Output Low Z ns t HZ Hold to Output High Z ns t DIS Output Disable Time Ns t EC Secter/Block/Chip Erase Time ms t PP Page Program Time ms t W Write Status Register Time ms t VCS V cc Set-up Time μs 2011 Genesys Logic, Inc. - All rights reserved. Page 29

30 7.6 On-Chip Power Regulator GL3520 requires 3.3V source power for normal operation of internal core logic and USB physical layer (PHY). The integrated low-drop power regulator converts 5V power input from USB cable (Vbus) to 3.3V voltage for silicon power source. The 3.3V power output is guaranteed by an internal voltage reference circuit to prevent unstable 5V power compromise USB data integrity. The regulator s maximum current loading is 250mA, which provides enough tolerance for normal GL3520 operation (below 100mA). On-chip Power Regulator Features: 5V to 3.3V low-drop power regulator 250mA maximum output driving capability Provide stable 3.3V output when Vin = 3.4V~5.5V 125uA maximum quiescent current (typical 80uA). Figure Vin(V5) vs Vout(V33)* *Note: Measured environment: Ambient temperature = 25 / Current Loading = 250mA 2011 Genesys Logic, Inc. - All rights reserved. Page 30

31 CHAPTER 8 PACKAGE DIMENSION Figure GL Pin QFN Package 2011 Genesys Logic, Inc. - All rights reserved. Page 31

32 Figure GL Pin QFN Package 2011 Genesys Logic, Inc. - All rights reserved. Page 32

33 CHAPTER 9 ORDERING INFORMATION Table Ordering Information Part Number Package Material Version Status GL3520-OVYXX QFN 88 Green Package XX Available GL3520-OSYXX QFN 64 Green Package XX Available 2011 Genesys Logic, Inc. - All rights reserved. Page 33

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GL852G is Genesys Logic’s premium 4-port Hub solution which fully complies with Universal Serial Bus Specification Revision 2.0. GL852G implements multiple TT* (Note1) architecture that provide dedicated TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL852G has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide.
GL852G implements multiple hub configuration features onto internal mask ROM, which traditionally requires one external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the initial stage to configure hub settings such as (1) number of DSport, (2) declare of compound device (3) gang/individual mode selection…etc. External EEPROM can be removed if no vendor specified PID/VID or product string is required for the application.
GL852G supports four package types, summarized as below table. LQFP48 package provides full hub features such as (1) two-color (green/amber) status LEDs for each DS ports, (2) Individual/Gang mode power management scheme that indicates DS port over-current events. (3) Number of DS ports setting configured by GPIO setting (4) non-removable declaration configured by GPIO setting (5) Support both 93C46 and 24C02 EEPROM (6) power switch polarity selections…etc. QFN28 package support only partial hub features but provide smaller footprint (5x5mm) that targets space limited PCB layout environments such as embedded system or UMPC/MID applications.

Package type	# of DS ports	Port # config.	Non-removable Declaration	Power mgmt.	LED support	EEPROM
48LQFP	4	GPIO	EEPROM/GPIO	Individual/Gang	Green/Amber	93C46/ 24C02
28QFN	4	EEPROM	EEPROM	Individual/Gang	N/A	24C02

*Note: TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the
unbalanced traffic speed between the upstream port and the downstream ports.

● Compliant to USB specification Revision 2.0
− 4 downstream ports
− Upstream port supports both high-speed (HS) and full-speed (FS) traffic
− Downstream ports support HS, FS, and low-speed (LS) traffic
− 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)
− Backward compatible to USB specification Revision 1.1
●On-chip 8-bit micro-processor
− RISC-like architecture
− USB optimized instruction set
− Dual cycle instruction execution
− Performance: 6 MIPS @ 12MHz
− With 64-byte RAM and 2K internal ROM
− Support customized PID, VID by reading external EEPROM
− Support downstream port configuration by reading external EEPROM
●Multiple Transaction translator (MTT)
− MTT provides respective TT control logics for each downstream port.
●Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0
●Built-in upstream port 1.5K0001 pull-up and downstream port 15K pull-down resistors
●Support both individual and gang modes of power management and over-current detection for downstream ports
●Conform to bus power requirements of USB 2.0 specification
●Automatic switching between self-powered and bus-powered modes
●Integrate USB 2.0 transceiver
●Embedded PLL support external 12 MHz crystal / Oscillator clock input
●Optional 27/48 MHz Oscillator clock input (Not available on QFN 28 package)
●Support compound-device (non-removable in downstream ports) by I/O pin configuration (Not available on QFN 28 package)
●Number of Downstream port can be configured by GPIO without external EEPROM (Not available on QFN 28 package)
●Operate on 3.3 Volts (Built-in 3.3V to 1.8V regulator)
●Improve output drivers with slew-rate control for EMI reduction
●Internal power-fail detection for ESD recovery
●Available package type: 48-pin LQFP and 28-pin QFN
●Applications:
− Stand-alone USB hub / USB Docking
− UMPC/MID, motherboard on-board applications
− Consumer electronics built-in hub application
− Monitor built-in hub
− Embedded systems
− Compound device to support USB HUB function such as keyboard hub applications